1. Field of the Invention
The invention relates to a method for controlling semiconductor chips, particularly memory chips, which are arranged in groups on modules. The invention also relates to a control apparatus for carrying out the method.
2. Description of the Related Art
Modern electronic systems normally comprise a multiplicity of semiconductor chips which are used as supports for integrated circuits. The large scale of integration achieved for these circuits using present methods allows a multiplicity of functions to be produced on a single semiconductor chip. Thus, by way of example, single dynamic memory chips (DRAMs) already contain more than 64 million individual memory cells.
Despite these large scales of integration, it is frequently necessary for functional units in electronic systems, such as the main memory in a computer system, to be made up of a plurality of individual components. In this case, the functional units are frequently distributed over a plurality of semiconductor chips which are then arranged in groups on modules.
There can be various reasons for using modules in this case. First, a modular design allows the use of relatively small semiconductor chips, which can normally be produced much less expensively. In addition, physical effects, such as the development of heat caused by power dissipation on the semiconductor chips, can make it appropriate to use a plurality of small units. Generally, using a modular design also allows flexible design of the corresponding functional device in the electronic system to be achieved.
To incorporate the semiconductor chips arranged on modules into the respective electronic system, bus systems are used which connect the semiconductor chips to corresponding components in the electronic system, such as to the central processor (central processing unit).
Particularly in modern electronic computer systems, whose main memory is generally constructed from a plurality of modules which each have a plurality of memory chips, a memory control unit (memory controller) undertakes connection of the memory chips to the common data bus. In this context, it forms a crucial component in the computer system, because its function involves controlling the data interchange between the processor and the memory.
Conventionally, memory chips in a module are firmly associated with a “bank” whose members simultaneously perform data interchange with the data bus. In this case, a bank comprises a particular number of memory chips in a module, the data lines of said memory chips together producing the exact word length of the corresponding data bus. This normally corresponds exactly to the number of memory chips arranged on a module. On account of the firm association for the memory chips, the memory control unit controls only the selection of firmly organized banks.
One problem which is found with the fixed organization of memory chips to form a bank, however, is that particularly the development of heat caused by the power dissipation in the memory chips can occur on a highly localized basis. In the case of some memory chips, a memory chip's rising temperature when heat develops (junction temperature) can then easily exceed a temperature which is critical for the respective semiconductor type, this being associated with a drastic increase in operating faults on the respective memory chip.
Since individual differences in the memory chips in a bank cannot be taken into account in the case of a firm bank organization, the development of heat, which is dependent on the respective degree of use and on the individual properties of a memory chip, normally results in an uneven temperature distribution in the memory chips along the corresponding module.
To prevent malfunctions in the memory chips, and hence to ensure a sufficiently high level of reliability for the memory chips, a module's memory chips which are firmly associated with a bank can be operated only at reduced power. This generally results in power losses for the entire memory.
To reduce power losses as a result of heat to which memory chips arranged on modules are subject, merely passive cooling elements are currently provided on the memory chips. Such passive cooling elements are described in JP 2001196516 A, JP 63299258 A, JP 63273342 A or JP 11354701 A, for example.